This invention broadly relates to data communications bit rate determining apparatus. The invention more particularly relates to apparatus and methods for automatically determining the bit rate of incoming signals and for determining when the bit rate has switched, when any of a plurality of bit rates may be received.
Various techniques have been used in data communication devices for determining the bit rate of an incoming signal where any of a plurality of data bit rates are to be accommodated, but the data rate is not previously known to the receiving apparatus. One technique, is to measure the pulse width of the incoming signal utilizing a much faster reference clock signal. By counting the number of reference clock cycles which fit within the incoming signal, a determination of the frequency of the incoming signal is made. Such a technique is effective as long as all permissible data rates are substantially different. However, where two data rates are close, due to jitter, the pulse which is measured may mistakenly appear to be the pulse of a clock signal at one rate when it actually is based on the second rate.
Phase locked loops are also used for measuring the rate of an incoming signal. Phase locked loops however, are most effective for monitoring and tracking small changes in signal rates. Where harmonics are involved (e.g. possible rates of 2400, 4800, 9600 bits/second), the phase locked loop is often ineffective, as a phase locked loop which is locked to a first frequency cannot detect a harmonic thereof which is by definition in phase therewith.